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1 PI3HDMI336 block diagram description PI3HDMI336 is an i 2 c confgurable active switch using pericoms new activeeye tm technology to achieve optimized sig - nal integrity for cable or on board transmission. trough i 2 c interface, system designer can easily program and adjust equalization, emphasis and output swing settings. with integrated ddc channel mux, hot plug detection de-mux, cable plug-unplug detection and hdmi 1.4 arc transmitter, PI3HDMI336 saves gpio control pins, provides optimized trace routing, and reduces bom cost. programmable tmds input termination settings helps designers to avoid the compatibility issue caused by non standard hdmi source. programmable output termination setting supports double ter - mination option between PI3HDMI336 and the hdmi receiver chip. tis feature minimizes the refection caused by improper impedance matching and reduces the signal jitter. PI3HDMI336 is hdmi 1.4 compatible with backward compat - ibility to the dvi 1.0 standard and can be used for the dp++ ap - plication devices. features ? ? hdmi 1.4 compliant with fast video switch among each ports ? ? i 2 c control 3:1 hdmi active switch mux with dc coupled or ac coupled dual mode displayport signals output will maintain its dc coupled, current- steering tmds compliance input can be ac coupled video or dc coupled ? ? 2.5gbps data rate for tmds clock up to 250mhz ? ? support up to 36-bits per pixel deep color tm modes ? ? programmable equalizer, emphasis and amplitude settings to achieve optimized hdmi signal integrity ? ? integrated selectable ddc active/ passive switch to connect ddc path ? ? idle clock detection function for output squelch ? ? programmable tmds termination control tmds input pull-up 50 ohm termination, pull-down >120k ohm resistor when switch is deselected double terminated tmds output ? ? integrated esd protection on i/o pins to connector 8kv contact per iec61000-4-2, level 3 ? ? packaging 64 pin lqfp (fb), pb-free and green 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ck - a ck + a d1- a d1+ a v dd d2- a d2+ a g nd d3- a d3+ a /o e int _ o ut s v dd s da _ct l s cl_ctl i 2 c_a dr d3+ c d3- c d2+ c d2- c v dd d1+ c d1- c g nd ck + c ck - c s cl_c s da _c hp d_c 5v _por ta 5v _por tb 5v _por tc a rc_ o ut s p dif _in v dd d3+ d3- d2 + d2- g n d d1+ d1- ck + ck - v dd s cl_s i nk s da _s i nk hp d_s i nk s cl_a s da _a hp d_a d3+ b d3- b d2+ b d2- b v dd d1+ b d1- b g nd ck + b ck - b s cl_b s da _b hp d_b p i 3h d mi 336 lq f p - 64 www.pericom.com 07/28/2012 12-0237
2 pin # pin name io descriptions 5, 19, 29, 44, 57 v dd power 3.3v power supply. when v dd is of, the tmds channels and arc will be powered down. 13 s vdd power 3.3v standby power supply. sv dd is for side band signals (hpd, ddc channel and the i 2 c control register unit). 8, 24, 41, 54 gnd ground ground connection 32 hpd_sink i sink side hot plug detector input; internal pull-down at 120k w . 62 hpd_a o port a hpd output 49 hpd_b o port b hpd output 36 hpd_c o port c hpd output 2 ck+a i port a tmds inputs. rt=50ohm; rpd=200k w . 1 ck-a 4 d1+a 3 d1-a 7 d2+a pin description hpd control & status register port a port b port c eq vdd r t rpd vdd r out vdd r t rpd vdd r t rpd port a tmds input ck+/-a,d1+/-[1..3] rt=50 ohm rpd = 200k ohm d+/- [1..3] ck+/- hpd_sink int_out arc_out /oe hpd_a hpd_b hpd_c port b tmds input ck+/-b,d2+/-[1..3] rt=50 ohm rpd = 200k ohm port c tmds input ck+/-c,d3+/-[1..3] rt=50 ohm rpd = 200k ohm scl_a, sda_a scl_b, sda_b scl_c, sda_c spdif_in scl/sda_sink scl/sda_ctl ddc buer or passive switch 5v_port[a..c] i2c controller mux mux block diagram www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
3 pin # pin name io descriptions 6 d2-a i port a tmds inputs. rt=50ohm; rpd=200k w . 10 d3+a 9 d3-a 53 ck+b i port b tmds inputs. rt=50ohm; rpd=200k w . 52 ck-b 56 d1+b 55 d1-b 59 d2+b 58 d2-b 61 d3+b 60 d3-b 40 ck+c i port c tmds inputs. rt=50ohm; rpd=200k w . 39 ck-c 43 d1+c 42 d1-c 46 d2+c 45 d2-c 48 d3+c 47 d3-c 27 ck+ o tmds outputs. rout=50 w . 28 ck- 25 d+1 26 d-1 22 d+2 23 d-2 20 d+3 21 d-3 64 scl_a io port a ddc clock 51 scl_b io port b ddc clock 38 scl_c io port c ddc clock 63 sda_a io port a ddc data 50 sda_b io port b ddc data 37 sda_c io port c ddc data pin description cont.. www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
4 pin# name io ty pe descriptions 30 scl_sink io sink side ddc clock 31 sda_sink io sink side ddc data 15 scl_ctl io i 2 c clock, compatible with i 2 c-bus specifcation, up to 400kb/s. 14 sda_ctl io i 2 c data, compatible with i 2 c-bus specifcation, up to 400kb/s. 12 int_out o interrupt pin. logic status output pin of int flag. open drain output, set int_out to high by external pull to sv dd resistor. 11 /oe i output enable control. active low. /oe only disables the high speed tmds channel but not the side band signals and i 2 c circuitry supplied by sv dd . internal pull-down at 100k ohm. 16 i 2 c_adr i i 2 c address lsb; internal pull-down at 100k w . 35, 34, 33 5v_ porta, 5v_ portb, 5v_ portc i connector 5v port. internal pull down resistor at 100k when v dd power on. 18 spdif_in i single mode arc signal input. see page 11 in detail. 17 arc_out o single mode arc signal output. pin description cont.. i 2 c address byte b7(msb) b6 b5 b4 b3 b2 b1 b0 (r/w) address - byte 1 0 1 0 1 0 i2c_adr 1/0 * i 2 c control register byte 0 bit descriptions ty pe power up condition logic settings 7 hdmi input port selection r/w 0 b[7:6] = 00 port a b[7:6] = 01 port b b[7:6] = 10 port c b[7:6] = 11 no port active see port selection truth table 6 hdmi input port selection r/w 0 5 tmds output enable r/w 1 0 = output disable disabled tmds channel and enter standby mode. side band signals and i 2 c circuitry are still alive. 1 = output enable see output enable control table www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
5 bit descriptions ty pe power up condition logic settings 4 hpd input selection r/w 0 0 = hpd_sink 1 = i 2 c register setting from b0b[0:3] under i2c register control mode, hpd[a:c] can be individually control by b0b[0:2] for hpd output. 3 hpd output stage selection r/w 0 0 = open drain 1 = output bufer 2 hpd port c logic setting r/w 0 i. byte0 b[4] = 1 when b0b[3] = 0 (open drain mode) b0b[2]=0, set hpd [c] to low b0b[2]=1, set hpd [c] to high by external pull high resistor when b0b[3] = 1 (output bufer mode) b0b[2]=0, set hpd [c] to high b0b[2]=1, set hpd [c] to low hpd port b logic setting r/w 0 i. byte0 b[4] = 1 when b0b[3] = 0 (open drain mode) b0b[1]=0, set hpd [b] to low b0b[1]=1, set hpd [b] to high by exter - nal pull high resistor when b0b[3] = 1 (output bufer mode) b0b[1]=0, set hpd [b] to high b0b[1]=1, set hpd [b] to low 0 hpd port a logic setting r/w 0 i. byte0 b[4] = 1 when b0b[3] = 0 (open drain mode) b0b[0]=0, set hpd [a] to low b0b[0]=1, set hpd [a] to high by exter - nal pull high resistor when b0b[3] = 1 (output bufer mode) b0b[0]=0, set hpd [a] to high b0b[0]=1, set hpd [a] to low www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
6 byte 1 bit descriptions ty pe power up condi - tion logic settings 7 port a rt , rpd on/of con - trol r/w 1 0 = rt disconnected, rpd connected 1 = rt connected, rpd disconnected 6 port b rt , rpd on/of control r/w 1 0 = rt disconnected, rpd connected 1 = rt connected, rpd disconnected 5 port c rt , rpd on/of control r/w 1 0 = rt disconnected, rpd connected 1 = rt connected, rpd disconnected 4 5v_portc connect r 0 0 = disconnected 1 = connected int flag b1b[1] is set by 5v_portc edge signal when 5v_portc changes from 1 to 0, or from 0 to 1. 3 5v_portb connect r 0 0 = disconnected 1 = connected int flag b1b[1] is set by 5v_portb edge signal when 5v_portb changes from 1 to 0, or from 0 to 1. 2 5v_porta connect r 0 0 = disconnected 1 = connected int flag b1b[1] is set by 5v_porta edge signal when 5v_porta changes from 1 to 0, or from 0 to 1 1 int flag r 0 0 = int flag clear 1 = int flag set int flag will be set from logic low to high, when any 5v_port has detected plug or unplug transition action. int flag is cleared to low afer i 2 c bus reads the register byte 1. see int flag fowchart. 0 ddc channel selection r/w 0 0 = passive switch 1 = active switch bufer for power saving operation, passive switch can be selected to fur - ther reduce the active power consumption. www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
7 byte 2 bit descriptions ty pe power up condition logic settings 7 tmds ac swing for cml output setting r/w 0 b[7:6] = 00 500mv *note 1 6 tmds ac swing for cml output setting r/w 0 5 tmds output pull-up resistor rout control r/w 0 0 = disconnect rout pull-up to v dd , open drain output 1 = connect rout pull-up to v dd (3.3v), double termina - tion output 4 output squelch control r/w 1 0 = output squelch disable 1 = output squelch enable *note 2, 3 3 tmds output pre-emphasis set - ting r/w 0 see ocx truth table 2 tmds output pre-emphasis set - ting r/w 0 see ocx truth table 1 tmds input equalization setting r/w 1 see eqx truth table 0 tmds input equalization setting r/w 0 see eqx truth table note: 1. b2[7:6] : internal use only 2. output squelch control is used to control tmds d+/-[0:3], which are set to high impedance /or pull-up to v dd by internal 50 w resistor when output squelch is enable if there is no tmds input signal. when squelch is disable, tmds d+/-[0:3] will be unknown if there is no tmds input signal. 3. squelch control is using clk channel signal detection. when tmds input clock frequency is low or swing is small, it will show no input signal. equalizer (eqx) truth table b2b[1] b2b[0] eq value on tmds data channels 0 0 3db 0 1 6db 1 0 12db (default) 1 1 16db tmds data channel only. tmds clock channels is 3db fxed www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
8 ocx truth table (swing setting b2b[7:6]=00, 500mv as default) tmds output pre-emphasis setting setting value note b2b[5] b2b[3] b2b[2] single-end vswing (mv) pre-emphasis (db) default setting 0 0 0 500 0 open drain 0 0 1 500 1.5 open drain 0 1 0 500 2.5 open drain 0 1 1 500 3.5 open drain 1 0 0 500 0 double termination 1 0 1 500 1.5 double termination 1 1 0 500 2.5 double termination 1 1 1 500 3.5 double termination port selection truth table b0b[7] b0b[6] tmds port ddc port 0 0 ck+/-a, d1+/-a,d2+/-a,d3+/-a scl_a/sda_a 0 1 ck+/-b, d1+/-b,d2+/-b,d3+/-b scl_b/sda_b 1 0 ck+/-c, d1+/-c,d2+/-c,d3+/-c scl_c/sda_c 1 1 no port active no port active data channel tmds input termination resistor rt, rpd control pull-down resistor rpd active conditions: 1. te data channel rt is disconnected controlled by byte 1 bit[7:5] 2. output enable control /oe is disable(/oe=high), pull down all channels 3. no normal operation voltage input (but standby voltage sv dd is still on), pull down all channels output enable control /oe i2c b0b[5] operation low high output enable x low output disable high x output disable note: output disable condition: tmds channel shut down, output high impedance. www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
9 int-flag fowchart p o w e r on r e s e t int - f l a g = 0 int - o u t = 0 ( p i n ) a n y 5 v - p o r t a /b /c f r o m h i g h to l o w o r f r o m l o w t o h i g h int - f l a g = 1 int - o u t = 1 ( p i n ) i 2 c r e a d o u t int - f l a g = 0 c o n d i ti o n : a f te r i 2 c r e a d o u t int - f l a g b i t a n d a c k f r o m m a s te r i s a c ti v e . i 2 c bus transactions data transfers follow the format shown in fig.1. afer the start condition (s), a slave address is sent. tis address is 7 bits long followed by an eighth bit which is a data direction bit (r/w) - a zero indicates a transmission (write), a one indicates a request for data (read). a data transfer is always terminated by a stop condition (p) generated by the master. however, if a master still wishes to communicate on the bus, it can generate a repeated start condition (sr) and address another slave without frst generat - ing a stop condition. various combinations of read/write formats are then possible within such a transfer. figure 1: a complete data transfer www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
10 data is transmitted to the PI3HDMI336 registers using the write mode as shown in figure 2. data is read from the PI3HDMI336 registers using the read mode as shown in figure 3 figure 2 : write to control register figure 3 : read from control register audio return channel tere are two arc input modes. teyre common mode input and single mode input but hdmi336 supports single mode input only. figure 1: arc single mode input and output www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
11 figure 2: arc single mode signal output waveform + v e h - sw i ng v e h - v e h - sw i n g + v e h -sw i ng - v e h - sw i n g v e h = 0~ 5v + v e h - sw i n g = 25 0m v - v e h - sw i n g = 25 0m v ddc channel application diagram 3 : 1 m u x s e l e c t a b l e d d c b u f f e r o r p a s s i v e s w i t c h s d a _ s i n k s c l _ s i n k c on t r ol l e r c h i p s c l _ a s d a _ a s c l _ b s d a _ b s c l _ c s d a _ c r u p r u p i2c block uses "low v il <= 0.4v and 0.7v <= 0.85v" to defne the signal direction, exit from system lock v ih > = 2 v v il = < 0 . 4 v v ol = 0 . 7 v / 0 . 85 v v ol = external ddc source side hdmi sink device www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
12 hpd[a:c] output diagram h pd o u tp u t b u ffe r 3 0 0 k o h m w e a k p u l l - d o wn no f r o m h p d _ s i n k o r i 2 c b y t e 0 [ 2 : 0 ] note: 1. hpd output block support by sv dd power. 2. during normal or standby mode, the hpd block is active. hpd signal output is programmed by the control register. 3. open drain bufer is recommended with a 1kohm pull-up resistor to 5v. if hpd output bufer is selected, external bufer transistor is required to avoid 5v to 3.3v leakage. hpd[a:c] truth table: b0b[4]=0, hpd_sink input; b0b[3]=0, hpdx open drain output port selection hpd input select b0b[4]=0 hpd output select b0b[3]=0 hpda hpdb hpdc port a hpd_sink open drain hpd_sink l l port b hpd_sink open drain l hpd_sink l port c hpd_sink open drain l l hpd_sink no port active hpd_sink open drain l l l b0b[4]=0, hpd_sink input; b0b[3]=1, hpdx inverter output port selection hpd input select b0b[4]=0 hpd output select b0b[3]=1 hpda hpdb hpdc port a hpd_sink bufer /hpd_sink h h port b hpd_sink bufer h /hpd_sink h port c hpd_sink bufer h h /hpd_sink no port active hpd_sink open drain h h h b0b[4]=1, i 2 c register input; b0b[3]=0, hpdx open drain output port selection hpd input select b0b[4]=1 hpd output select b0b[3]=0 hpda hpdb hpdc b0b[3]=0 hpda hpdb hpdc port [a:c] b0b[2:0] open drain b0b[0] b0b[1] b0b[2] no port active b0b[2:0] open drain b0b[0] b0b[1] b0b[2] www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
13 b0b[4]=1, i2c register input; b0b[3]=1, hpdx inverter output port selection hpd input select b0b[4]=1 hpd output select b0b[3]=1 hpda hpdb hpdc port [a:c] b0b[2:0] bufer /b0b[0] /b0b[1] /b0b[2] no port active b0b[2:0] bufer /b0b[0] /b0b[1] /b0b[2] absolute maximum ratings supply voltage to ground potential ................................................... 5.5v all inputs and outputs ................................................ -0.5v to v dd +0.5v ambient operating temperature ........................................... -20 to +85c storage temperature ............................................................ -65 to +150c junction temperature ....................................................................... 150c soldering temperature ..................................................................... 260c recommended operation conditions parameter min. ty p. max. unit ambient operating temperature -20 +85 c power supply voltage (measured in respect to gnd) +3.0 +3.6 v dc specification v dd = 3.3v 10%, symbol parameter conditions min. ty p. max. unit v dd operating voltage 3.0 3.3 3.6 v i dd v dd supply current output enable ( open drain 500mv signal-end 0db pre-emphasis) 80 92 ma output enable ( double termination, 500mv signal-end 0db pre-emphasis) 170 210 ma i ddq v dd quiescent sup - ply current tmds output disable, arc_out=0 3 ma istb standby mode v dd = 0v, s vdd =3.6v, ddc passive switch, hpd_x=0 1 ma v ih _ 5v_ a, v ih _ 5v_ b, v ih _ 5v_c input high voltage of 5v ports 0.7*sv dd v v il _ 5v_ a, v il _ 5v_ b, v il _ 5v_c input low voltage of 5v ports 0.3*sv dd v note: s tresses greater than those listed under maxi - mum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maxi - mum rating conditions for extended periods may afect reliability. www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
14 symbol parameter conditions min. ty p. max. unit v ol_hpd bufer output low voltage i ol = 4 ma 0.4 v open drain output l ow voltage i ol = 4 ma 0 0.4 v v oh_hpd bufer output high voltage i oh = 1 ma sv dd -1.1 v i off_hpd of leakage current v dd =0, sv dd =0, v in =3.6v 10 ua v dd =0, sv dd =0, v in =5.5v 20 i oz_hpd open drain output leakage current s vdd =3.6, v in =3.6v 25 s vdd =3.6, v in =5.5v 35 hpd_sink i ih high level digital input current v ih =v dd -10 40 a i il low level digital input current v il = gnd -10 10 a v ih high level digital input voltage sv dd =3.3v 2.0 v v il low level digital input voltage 0 0.8 v control pin (/oe) i ih high level digital input current v ih =v dd -10 40 a i il low level digital input current v il = gnd -10 10 a v ih high level digital input voltage 2.0 v v il low level digital input voltage 0 0.8 v int_out v ol_int_out output open drain l ow voltage i ol = 4 ma 0.4 v v oh_int_out high impedance, depended on external pull high resistor and power supplier external pull-up rup to v dd from 1.5k to 5k v dd -1 v i off_int_out of leakage current v dd =0, sv dd =0, v in =3.6v 10 ua v dd =0, sv dd =0, v in =5.5v 20 dc specification cont.. www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
15 ddc channel block symbol parameter conditions min. ty p. max. unit v ih_ddc(source) source side ddc bufer input hig h voltage 0.7*sv dd v v il _ddc(source) source side ddc bufer input l ow voltage 0.3*sv dd v v ol _ddc(source) source side ddc bufer out - put low voltage, external pull-up rup to v dd from 1.5k to 5k 0.4 v v ol_ddc(sink) sink side ddc bufer output l ow voltage, external pull-up rup to v dd from 1.5k to 5k 0.7 0.85 v v ih_ddc(sink) sink side ddc bufer input hig h voltage, 2.0 v v il _ddc(sink) sink side ddc bufer input l ow voltage, 0.4 v i lk input leakage current ddc switch is of -10 10 ua c io input/output capacitance when passive switch on vi peak-peak = 1v, 100 khz 10.5 pf r on passive switch resistance io = 3ma, v o = 0.4v 30 50 vpass switch output voltage v i =3. 3v, i i=10 0 u a sv dd =3.3v 1.5 2.0 2.8 v ci(source) source side ddc capacitance when active switch on or pas - sive switch of. v i peak-peak = 1v, 100 khz 4.0 pf ci(sink) sink side ddc capacitance when active switch on or pas - sive switch of. v i peak-peak = 1v, 100 khz 6.0 pf v oh_ddc (source/sink) ddc switch output high voltage v in =3. 3v. external pull-up rup to v dd from 1.5k to 5k v dd - 1 v www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
16 ac characteristics (over recommended operating conditions unless otherwise noted) symbol parameter test conditions min. ty p.(1) max. units tmds diferential pins t pd propagation delay v dd = 3.3v, rout = 50 2000 ps t r diferential output signal rise time (20% - 80%) 150 t f diferential output signal fall time (20% - 80%) 150 t sk(p) pulse skew 10 50 t sk(d) intra-pair diferential skew 23 50 t sk (o) inter-pair diferential skew (2) 100 t jit (pp) peak-to-peak output jitter clk residual jitter data input = 1.65 gbps hdmi data pattern clk input = 165 mhz clock 15 30 ps t jit (pp) peak-to-peak output jitter data residual jitter 18 50 ps t sx select to switch output 10 ns t en enable time 600 ns t dis disable time 10 ns ddc i/o pins (scl, scl_sink, sda, sda_sink) t pd propagation delay from scln to scl_sink or sdan to sda_ sink or sda_sink to sdani in passive or active sw. c l = 10pf, in passive switch 1.5 2.5 ns c l = 10pf, in active switch, svdd=3.3v, rup=2k 7.5 ddc i/o pins (hpd_sink, hpd inverter output) *note 1 t pd (hpd) propagation delay (from hpd_ sink to the active port of hpd) c l = 10pf 2 6.0 ns t sx (hpd) switch time (from port select to the latest ) 3 6.5 note: 1. t plh time of hpd open drain output, depends on external pull high resistor and load capacitor. www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
17 tmds diferential pins symbol parameter test conditions min. ty p. max. units v oh single-ended high level output voltage v dd = 3.3v, rout=50 v dd +10 v dd -10 mv v ol single-ended low level output voltage v dd -600 v dd C400 mv vsw ing single-ended output swing voltage 400 600 mv v od(o) overshoot of output diferential voltage 180 1 mv v od(u) undershoot of output diferential volt - age 200 2 mv v oc(ss) change in steady-state common- mode output voltage between logic states 5 mv i os short circuit output current -12 12 ma short circuit output current at double termination mode -24 24 ma vi(open) single-ended input voltage under high impedance input or open input i i = 10ua v dd -10 v dd +10 mv r t input termination resistance v in = 2.9v 45 50 55 ohm i oz leakage current with hi-z i/o v dd = 3. 6 v, sv dd = 3.6v 10 a spdif & arc pins, see arc single mode waveform symbol parameter test conditions min. ty p. max. units i ih _spdif high level input current v dd =3. 6 v, v ih =3.6v 500 ua i il _spdif low level input current v dd =3. 6 v, v il = gnd 350 ua vel single mode input/output vel dc volt - age level 0 5.0 v vel swing spdif single mode input swing 0.2 0.6 v vel swing arc_ out single mode arc output swing 0.4 0.5 0.6 v ro output resistance of arc output stage 55 ohm t r arc output rise time (10% to 90%) < 0.4ui (f clock = 6.144mhz) ** 25 ns tf arc output fall time (10% to 90%) < 0.4ui (f clock = 6.144mhz) ** 25 ns tjpp arc signal peak to peak jitter < 0.05ui (f clock = 6.144mhz) 3 ns note: 1. overshoot of output diferential voltage v od (o) = (vswing(max) * 2) * 15%, 2. undershoot of output diferential voltage v od (o) = (vswing(min) * 2) * 25% www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
18 pericom semiconductor corporation ? 1-800-435-2336 packaging mechanical: 64-pin lqfp (fb) da te: 05/18/11 description: 64-contact, low profile quad flat package (lqfp) p ackage code: fb (fb64) document control #: pd-2099 revision: -- notes: 1. 1. jedec outline: ms-026 bbd 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. 11-0064 www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
19 related products part number product description pi3hdmi1201 displayport 1.2 re-driver with built-in aux listener pi3vdp1430 dual mode displayport to hdmi level shifer and re-driver pi3hdmi511 3.4g hdmi1.4 re-driver for source-side application, supporting dual mode displayport pi3hdmi611 3.4g hdmi1.4 re-driver for sink-side application, supporting dual mode displayport pi3vdp3212 2-lane displayport1.2 compliant switch pi3vdp12412 4-lane displayport1.2 compliant switch pi3hdmi412ad 1:2 active 3.4gbps hdmi1.4 compliant splitter/re-driver pi3hdmi521 2:1 3.4gbps hdmi1.4 switch/re-driver with built-in arc and fast switching support for sink application pi3hdmi621 2:1 3.4gbps hdmi1.4 switch/re-driver with built-in arc and fast switching support for sink application PI3HDMI336 3:1 active 3.4gbps hdmi switch/re-driver with i 2 c control and arc transmitter reference information document description vesa vesa displayport standard version 1 revision 2, video electronics standards association, january 5, 2010 vesa displayport dual-mode standard version 1, video electronics standards association, february 10, 2012 vesa displayport interoperability guideline version 1.1a, video electronics standards association, febru - ary 5, 2009 hdmi high-defnition multimedia interface specifcation version 1.4, hdmi licensing, llc, june 5, 2009 ordering information ordering code package code pack age ty pe PI3HDMI336fbe fb pb-free & green, 64-pin lqfp 1. termal characteristics can be found on the company web site at www.pericom.com/packaging/ www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
20 revision history date changes 7/28/2012 block diagram, reference schematic www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
21 appendix: eye diagram at 1920x1080p input: quantum data + hdmi cable dut setting: selected port = port c; hpd = open drain; tmds = open drain/cml, rt connected, 500mv, 0db pre-emphasis output: hdmi-sma test fixture + agilent 54855a dso d1 eye at 1920x1080p 12bit, 12db eq, 2m cable, open drain d1 eye at 1920x1080p 12bit, 12db eq, 10m cable, open drain d1 eye at 1920x1080p 8bit, 12db eq, 20m cable, open drain d1 eye at 1920x1080p 8bit, 16db eq, 30m cable, open drain www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237
22 appendix: reference schematic 5 5 4 4 3 3 2 2 1 1 d d c c b b a a scl_b sda_b scl_a sda_a scl_c sda_c ck+_a scl_ctl d0+_b d1-_b +5v_b d0-_a d1+_b d0+_a d2+_c d0+_a d2-_b d1-_b d1-_a d2-_c d2+_b hpd_b d2-_b d1+_a d1+_c +5v_a d1-_a d2+_b d2-_a d1-_c sda_b +5v_b d2+_a d0+_c +5v_c hpd_b int_out d1+_a d0-_c /oe i2c_adr scl_b scl_a +5v_c scl_c d2+_c d2-_a ck+_c d2-_c ck-_c d1+_c d2+_a ck-_d d1-_c spdif_in ck+_d d0+_c d0-_d sda_c d0-_c d0+_d scl_c ck+_c d1-_d sda_a d1+_d ck-_c hpd_a +5v_a d2-_d ck-_a hpd_c d2+_d sda_c hpd_c sda_b sda_a scl_b hpd_a arc_out scl_a ck-_b ck-_b ck+_b ck+_a ck+_b d0-_b ck-_a d0-_b sda_ctl d0+_b d0-_a hpd_sink sda_sink scl_sink +5v_usb +5v_c +5v_b +5v_a scl_sink sda_sink +5v_d cec_d ck-_d ck+_d d0-_d d0+_d d1-_d d1+_d d2-_d d2+_d +5v_d spdif_in arc_out hpd_sink +5v_a +5v_b +5v_c edid_wpa edid_wpb edid_wpc cec_d cec_d cec_d spdif_in arc_out int_out scl_a sda_a scl_b sda_b scl_c sda_c scl_ctl sda_ctl edid_wpa edid_wpb edid_wpc d1+_b +5v_b +5v_a +5v_c +3v3sb +3v3 +5v +3v3 +3v3 +3v3sb +3v3sb +5v +3v3sb +3v3 +3v3 +3v3 +3v3sb title size document number rev date: sheet of a PI3HDMI336_demoboard_independent_edid c 11 thursday, january 13, 2011 title size document number rev date: sheet of a PI3HDMI336_demoboard_independent_edid c 11 thursday, january 13, 2011 title size document number rev date: sheet of a PI3HDMI336_demoboard_independent_edid c 11 thursday, january 13, 2011 i2c_address a0 0xa8 0xaa 0 1 /oe is pulled down at 100k ohm. i2c_adr is pulled up at 100k ohm. power hpd output open drain output buffer connection jp212: 2-3 jp212: 2-1 jp213: 2-3 jp213: 2-1 jp214: 2-3 jp214: 2-1 c206 0.1u c206 0.1u jp204 jp204 1 2 r212 4k7 r212 4k7 r227 100k r227 100k u201 PI3HDMI336 u201 PI3HDMI336 ck-a 1 ck+a 2 d1-a 3 d1+a 4 vdd 5 d2-a 6 d2+a 7 gnd 8 d3-a 9 d3+a 10 /oe 11 int_out 12 svdd 13 sda_ctl 14 scl_ctl 15 i2c_adr 16 arc_out 17 spdif_in 18 vdd 19 d3+ 20 d3- 21 d2+ 22 d2- 23 gnd 24 d1+ 25 d1- 26 ck+ 27 ck- 28 vdd 29 scl_sink 30 sda_sink 31 hpd_sink 32 5v_portc 33 5v_portb 34 5v_porta 35 hpd_c 36 sda_c 37 scl_c 38 ck-c 39 ck+c 40 gnd 41 d1-c 42 d1+c 43 vdd 44 d2-c 45 d2+c 46 d3-c 47 d3+c 48 hpd_b 49 sda_b 50 scl_b 51 ck-b 52 ck+b 53 gnd 54 d1-b 55 d1+b 56 vdd 57 d2-b 58 d2+b 59 d3-b 60 d3+b 61 hpd_a 62 sda_a 63 scl_a 64 jp205 jp205 1 2 q205 mmbt3904 q205 mmbt3904 1 2 3 jp209 jp209 1 2 input3 conn_hdmi-r input3 conn_hdmi-r d2+ 1 d2 shield 2 d2- 3 d1+ 4 d1 shield 5 d1- 6 d0+ 7 d0 shield 8 d0- 9 ck+ 10 ck shield 11 ck- 12 cec 13 heac+ 14 scl 15 sda 16 pgnd 17 +5v 18 hpd 19 shell1 20 shell3 22 shell2 21 shell4 23 r206 47k r206 47k jp202 jp202 1 2 r214 4k7 r214 4k7 jp216 jp216 1 2 d205 led_g d205 led_g 1 2 r228 np r228 np d203 b0520lw d203 b0520lw c211 0.1u c211 0.1u r204 1k r204 1k r219 4k7 r219 4k7 q204 mmbt3904 q204 mmbt3904 1 2 3 input1 conn_hdmi-r input1 conn_hdmi-r d2+ 1 d2 shield 2 d2- 3 d1+ 4 d1 shield 5 d1- 6 d0+ 7 d0 shield 8 d0- 9 ck+ 10 ck shield 11 ck- 12 cec 13 heac+ 14 scl 15 sda 16 pgnd 17 +5v 18 hpd 19 shell1 20 shell3 22 shell2 21 shell4 23 input2 conn_hdmi-r input2 conn_hdmi-r d2+ 1 d2 shield 2 d2- 3 d1+ 4 d1 shield 5 d1- 6 d0+ 7 d0 shield 8 d0- 9 ck+ 10 ck shield 11 ck- 12 cec 13 heac+ 14 scl 15 sda 16 pgnd 17 +5v 18 hpd 19 shell1 20 shell3 22 shell2 21 shell4 23 jp213 jp213 1 2 3 d208 led_g d208 led_g 1 2 r202 47k r202 47k r213 4k7 r213 4k7 jp201 jp201 1 2 c212 4.7u c212 4.7u q201 mmbt3904 q201 mmbt3904 1 2 3 u202 at24c02b u202 at24c02b a2 3 a0 1 sda 5 gnd 4 a1 2 scl 6 wp 7 vcc 8 r218 4k7 r218 4k7 c207 1u c207 1u j0 usb 2.0 mini b female j0 usb 2.0 mini b female vbus 1 d- 2 d+ 3 id 4 gnd 5 c214 1u c214 1u u203 at24c02b u203 at24c02b a2 3 a0 1 sda 5 gnd 4 a1 2 scl 6 wp 7 vcc 8 jp208 jp208 1 2 r215 4k7 r215 4k7 r201 1k r201 1k d207 led_g d207 led_g 1 2 r203 47k r203 47k r224 68k r224 68k r225 1k r225 1k r205 47k r205 47k r207 1k r207 1k r216 1k/ nc r216 1k/ nc j2 rca jack j2 rca jack 1 2 r208 47k r208 47k r210 4k7 r210 4k7 d202 b0520lw d202 b0520lw q203 mmbt3904 q203 mmbt3904 1 2 3 jp211 jp211 1 2 c205 0.1u c205 0.1u c215 1u c215 1u u205 reg1117-3.3v u205 reg1117-3.3v adj/gnd 1 vout 2 vin 3 c209 0.1u c209 0.1u r231 10k r231 10k r222 68k r222 68k r221 1k r221 1k c208 1u c208 1u c203 0.1u c203 0.1u c204 0.1u c204 0.1u r220 55 r220 55 u204 at24c02b u204 at24c02b a2 3 a0 1 sda 5 gnd 4 a1 2 scl 6 wp 7 vcc 8 q206 mmbt3904 q206 mmbt3904 1 2 3 jp215 jp215 1 2 3 jp207 jp207 1 2 c210 0.1u c210 0.1u + c213 100u + c213 100u r229 0 r229 0 jp203 jp203 1 2 jp206 jp206 1 2 jp217 jp217 1 2 jp214 jp214 1 2 3 d201 b0520lw d201 b0520lw jp210 jp210 1 2 r209 47k r209 47k l1 ferritebead_1206 l1 ferritebead_1206 1 2 d206 led_g d206 led_g 1 2 j1 rca jack j1 rca jack 1 2 r211 4k7 r211 4k7 r232 10k r232 10k d204 b0520lw d204 b0520lw + c216 22u + c216 22u r223 1k r223 1k jp212 jp212 1 2 3 q202 mmbt3904 q202 mmbt3904 1 2 3 r226 68k r226 68k r230 10k r230 10k c201 0.1u c201 0.1u output conn_hdmi-r output conn_hdmi-r d2+ 1 d2 shield 2 d2- 3 d1+ 4 d1 shield 5 d1- 6 d0+ 7 d0 shield 8 d0- 9 ck+ 10 ck shield 11 ck- 12 cec 13 heac+ 14 scl 15 sda 16 pgnd 17 +5v 18 hpd 19 shell1 20 shell3 22 shell2 21 shell4 23 r217 1k r217 1k c202 0.1u c202 0.1u appendix: evaluation board image www.pericom.com 07/28/2012 PI3HDMI336 3:1 activeeye? hdmi? switch with i 2 c control & arc transmitter 12-0237

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